--
--  nvtop_o.vhd
--
--  Top entitiy of nikuvdp.vhd (for ese-pld ohkoshi version).
--
--        Copyright (C)2000,2001 Kunihiko Ohnaka
--                   All rights reserved.
--
-- $Id:$
--

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity nvtop_o is
  port(
-- Video Engine Clock (21.477MHz)
    pVideoClk   : in std_logic;

-- MSX Slot Signals
    pSltClk     : IN std_logic;
    pSltRst_n   : IN std_logic;
    pSltSltsl_n : IN std_logic;
    pSltIorq_n  : IN std_logic;
    pSltRd_n    : IN std_logic;
    pSltWr_n    : IN std_logic;
    pSltAdr     : IN std_logic_vector(15 downto 0);
    pSltDat     : INOUT std_logic_vector(7 downto 0);
    pSltBdir_n  : OUT std_logic;
    pSltCs1     : IN std_logic;
    pSltCs2     : IN std_logic;
    pSltCs12    : IN std_logic;
    pSltRfsh_n  : IN std_logic;
    pSltWait_n  : IN std_logic;
    pSltInt_n   : INOUT std_logic;
    pSltM1_n    : IN std_logic;
    pSltMerq_n  : IN std_logic;
--    pSltClk2    : IN std_logic;
--    pSltRsv5    : OUT std_logic;
--    pSltRsv516   : OUT std_logic;

-- 2 sram address
    pRamAdrX    : OUT std_logic_vector(18 downto 0);
    pRamAdrY    : OUT std_logic_vector(18 downto 0);

-- Graphic Piece Controller (GPC) signals.
    pRamCeX_n   : OUT std_logic;
    pRamOeX_n   : OUT std_logic;
    pRamWeX_n   : OUT std_logic;
    pRamDataX    : INOUT std_logic_vector(7 downto 0);
    pRamCeY_n   : OUT std_logic;
    pRamOeY_n   : OUT std_logic;
    pRamWeY_n   : OUT std_logic;
    pRamDataY    : INOUT std_logic_vector(7 downto 0);

-- Video Output
    -- Video DAC(MB40988) clock
--    pVDACClk   : OUT std_logic;

    -- 18bit digital color output
    pVideoR	: OUT std_logic_vector( 5 downto 0);
    pVideoG	: OUT std_logic_vector( 5 downto 0);
    pVideoB	: OUT std_logic_vector( 5 downto 0);

    -- Sync Signals
    pVideoHS_n	: OUT std_logic;
    pVideoVS_n	: OUT std_logic;
    pVideoCS_n	: OUT std_logic;

    -- CXA1645(RGB->NTSC Encoder) clock and signal.
    pVideoSC	: OUT std_logic;
    pVideoSYNC  : OUT std_logic;

-- test pins
    pTest0       : OUT std_logic;
    pTest1       : OUT std_logic

    );
end nvtop_o;

architecture RTL of nvtop_o is
  component NIKUVDP
    port(
-- Video Engine Clock (21.477MHz)
    pVideoClk   : in std_logic;

-- MSX Slot Signals
    pSltClk     : IN std_logic;
    pSltRst_n   : IN std_logic;
    pSltSltsl_n : IN std_logic;
    pSltIorq_n  : IN std_logic;
    pSltRd_n    : IN std_logic;
    pSltWr_n    : IN std_logic;
    pSltAdr     : IN std_logic_vector(15 downto 0);
    pSltDat     : INOUT std_logic_vector(7 downto 0);
    pSltBdir_n  : OUT std_logic;
    pSltCs1     : IN std_logic;
    pSltCs2     : IN std_logic;
    pSltCs12    : IN std_logic;
    pSltRfsh_n  : IN std_logic;
    pSltWait_n  : IN std_logic;
    pSltInt_n   : INOUT std_logic;
    pSltM1_n    : IN std_logic;
    pSltMerq_n  : IN std_logic;
--    pSltClk2    : IN std_logic;
--    pSltRsv5    : OUT std_logic;
--    pSltRsv516   : OUT std_logic;


-- Graphic Piece Controller (GPC) signals.
    pRamAddr    : OUT std_logic_vector(18 downto 0);
    pRamCeX_n   : OUT std_logic;
    pRamOeX_n   : OUT std_logic;
    pRamWeX_n   : OUT std_logic;
    pRamDataX    : INOUT std_logic_vector(7 downto 0);
    pRamCeY_n   : OUT std_logic;
    pRamOeY_n   : OUT std_logic;
    pRamWeY_n   : OUT std_logic;
    pRamDataY    : INOUT std_logic_vector(7 downto 0);

-- Video Output
    -- Video DAC(MB40988) clock
    pVDACClk   : OUT std_logic;

    -- 18bit digital color output
    pVideoR	: OUT std_logic_vector( 5 downto 0);
    pVideoG	: OUT std_logic_vector( 5 downto 0);
    pVideoB	: OUT std_logic_vector( 5 downto 0);

    -- Sync Signals
    pVideoHS_n	: OUT std_logic;
    pVideoVS_n	: OUT std_logic;
    pVideoCS_n	: OUT std_logic;

    -- CXA1645(RGB->NTSC Encoder) clock and signal.
    pVideoSC	: OUT std_logic;
    pVideoSYNC  : OUT std_logic;

-- test pins
    pTest0       : OUT std_logic;
    pTest1       : OUT std_logic

        );
  end component;
    
  signal SramAddr : std_logic_vector(18 downto 0);
  signal VDACClk : std_logic;      
begin 
    -------------------------------------------------------------------------------
    -- Connect Components
    -------------------------------------------------------------------------------
    nikuvdp1 : NIKUVDP
        port map(
            pVideoClk  ,
            pSltClk    ,
            pSltRst_n  ,
            pSltSltsl_n,
            pSltIorq_n ,
            pSltRd_n   ,
            pSltWr_n   ,
            pSltAdr    ,
            pSltDat    ,
            pSltBdir_n ,
            pSltCs1    ,
            pSltCs2    ,
            pSltCs12   ,
            pSltRfsh_n ,
            pSltWait_n ,
            pSltInt_n  ,
            pSltM1_n   ,
            pSltMerq_n ,
            SramAddr   ,
            pRamCeX_n  ,
            pRamOeX_n  ,
            pRamWeX_n  ,
            pRamDataX   ,
            pRamCeY_n  ,
            pRamOeY_n  ,
            pRamWeY_n  ,
            pRamDataY   ,
            VDACClk  ,
            pVideoR,
            pVideoG,
            pVideoB,
            pVideoHS_n,
            pVideoVS_n,
            pVideoCS_n,
            pVideoSC,
            pVideoSYNC ,
            pTest0      ,
            pTest1
            );

--
--  asyncronous connections
--  
    pRamAdrY <= SramAddr;
    pRamAdrX <= SramAddr;

end RTL;